中文摘要：

采用标准0．18μmCMOS工艺，设计了一种连续速率时钟与数据恢复（CDR）电路。该CDR电路主要由半速率鉴频鉴相器、多频带环形压控振荡器、电荷泵和判决电路等模块组成。其中，半速率鉴频鉴相器主要由四个双边沿触发器组成，结构简单，功耗和面积相应降低。多频带环形压控振荡器同时满足了较宽的调谐范围和较低的调谐增益，可以解决高振荡频率和低调谐增益之间的矛盾。电荷泵采用增益自举共源共栅放大器和互补开关电路结构，减小了各种非理想因素的影响。并行判决电路实现数据的1：2分接输出。仿真结果表明，该CDR电路能正常恢复622～3125Mbit／s的伪随机数据。版图尺寸为691μm×543μm。在1．8V电源电压下，输入伪随机速率3125Mbit／s时，功耗为120mW，恢复出的数据和时钟的抖动峰峰值分别为5．18和4．41ps。

英文摘要：

A continuous-rate clock and data recovery （CDR） circuit was designed by the standard 0. 18 μm CMOS process, which was mainly composed of a half-rate phase frequency detector （PFD） , a multi-band ring voltage-controlled oscillator （VCO）, a charge pump （CP）, a decision circuit and other blocks. The half-rate PFD consisted of four double-edge flip-flops, which had a simple structure , accordingly, both the power consumption and die area were reduced . Both wide tuning range and low tuning gain were satisfied by the Multi-band ring VCO, which could deal with the conflict between a high oscillating frequency and a low tuning gain. Various non-ideal effects are reduced by the CP with a gain- boosted cascode amplifier and acomplementary-switch structure. Besides, the parallel decision circuit has the function of a 1：2 demuhipexer. Finally, simulation results show that the CDR circuit can recover the non return to zero （NRZ） data from 622 to 3 125 Mbit/s. The core size is 691 μm × 543 μm, When a pseudo random bit stream （PRBS） data of 3 125 Mbit/s is input under the supply voltage of 1.8 V, the power consumtion is 120 mW, and the peak-to-peak jitter of the recovered data and clock are 5. 18 and 4.41 ps, respectively.