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中文摘要：
为减少三维芯核绑定前和绑定后的测试时间,降低测试成本,提出了基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法.所提方法首先通过最大化每条测试外壳扫描链的跨度,使得绑定前高层电路和低层电路的测试外壳扫描链数量尽可能相等.然后,在TSVs（Through Silicon Vias）数量的约束下,逐层的将虚拟层中的扫描元素分配到测试外壳扫描链中,以平衡绑定前后各条测试外壳扫描链的长度.实验结果表明,所提方法有效地减少了三维芯核绑定前后测试的总时间和硬件开销.
英文摘要：
To reduce test lime and test cost for pre-bond and post-bond test of three dimensional embedded cores,this paper proposed an optimization method based on span and virtual layers for wrapper scan chains in three dimensional embedded cores. Firstly, the proposed technique made the number of wrapper scan chains in high layers and low layers as equal as possible by maxi- mizing the span of wrapper scan chains. Then, under the constraints of TSVs（Through Silicon Vias）number, the scan elements con- tained in virtual layers were assigned to wrapper scan chains layer by layer, which effectively balanced the length of pre-bond and post-bond wrapper chains. Experimental results show the presented methodology can greatly reduce the pre-bond/post-bond test time and hardware overhead for three dimensional embedded cores.
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