中文摘要：

实现是重要挑战一低 -- 费用力量分析免疫者先进加密标准(AES ) 电路。以前的学习证明在 AES 的盒子(S 盒子) 是的那替换对被攻击敏感、难为它的非线性的特征掩盖。而且，在薄片的大量电路资源和电源消费在保护 S 盒子免于电源分析被花。因此，一个新奇电源分析免疫者计划被建议，它把 AES 的数据路径划分成二部分：不同类的 S 盒子随机被选择而不是固定 S 盒子在非线性的模块中扰乱电源和逻辑延期；同时，一般掩盖策略在 AES 的线性部分被使用。这个改进 AES 电路与统一微电子学公司(UMC ) 被综合 0.25 m 1.8 V 互补 metal-oxide-semiconductor (互补金属氧化物半导体) 标准分析试验的房间图书馆，和关联电源被执行。结果证明这安全 AES 实现让很低的硬件对电源分析有效地花费了并且能提高 AES 安全。

英文摘要：

It is an important challenge to implement a lowcost power analysis immune advanced encryption standard （AES） circuit. The previous study proves that substitution boxes （S-Boxes） in AES are prone to being attacked, and hard to mask for its non-linear characteristic. Besides, large amounts of circuit resources in chips and power consumption are spent in protecting S-Boxes against power analysis. Thus, a novel power analysis immune scheme is proposed, which divides the data-path of AES into two parts： inhomogeneous S-Boxes instead of fixed S-Boxes are selected randomly to disturb power and logic delay in the non-linear module; at the same time, the general masking strategy is applied in the linear part of AES. This improved AES circuit was synthesized with united microelectronics corporation （UMC） 0.25 μm 1.8 V complementary metal-oxide-semiconductor （CMOS） standard cell library, and correlation power analysis experiments were executed. The results demonstrate that this secure AES implementation has very low hardware cost and can enhance the AES security effectually against power analysis.