中文摘要：

基于级间密勒补偿技术,产生一个低频主极点,并通过阻尼系数控制（DFC）单元调节两个次主极点略高于单位增益频率（UGF）,使得无电容型LDO开环传递函数中在UGF内只有一个极点,从而保证环路稳定性,同时又优化了系统的动态响应.基于该结构,采用HHNEC0.25μm CMOS工艺,设计了一个1.8V100mA的适合SoC应用的无电容型LDO.其电压降为50mV,在50μA到100mA的负载电流范围内,开环传递函数相位裕度高于55度,瞬态电压过冲值低于140mV,负载电流在最大值与最小值之间阶跃变化时,最大恢复时间为3μs,系统静态电流为40μA.

英文摘要：

By using Miller compensation, a lower frequency dominant pole is generated, and two other no-dominant poles, which frequency are higher than unity gain frequency （UGF）, can be configured by Damping Factor Control （DFC） block. Single pole system is formed before UGF and satisfied phase margin is revealed, hence the stability and good transient performance are ensured. A 1.8V 100mA capacitor-less LDO for SoC application is targeted by HHNEC 0.25μm standard CMOS process in this paper. Simulation shows that the dropout voltage is 50mV, phase margin achieves better than 55°among all allowed load current, and output overshoot is less than 140mV while recovering time is about 3μs for full load current changes. Total supply current of 40 μA caters to SoC low power application.