中文摘要：

在无线通讯的微电子学技术和进展的最近的发展使为无线传感器网络(WSN ) 设计便宜、低力量、多功能、聪明的传感器节点可行。为有效 WSN 的设计挑战主要在二个问题躺着：力量和安全。Rijindael 算法是为在 WSN 加密数据的一个候选人算法。SubByte (S 盒子) 转变是 Rijindael 算法的主要积木。它统治硬件复杂性和 Rijindael 密码的引擎的电源消费。这篇文章建议 S 盒子的钟更少硬件实现。在这 S 盒子， 1 ) 在 GF 的合成的地算术((24 )) 2 被用来实现紧缩的 datapath 电路；2 ) 一个高效率的门闩控制器被利用四阶段的 micropipeline 达到。介绍硬件电路是一个应用程序 0.25 m 上的特定的集成电路(ASIC ) 用三金属层的互补心理氧化物半导体(互补金属氧化物半导体) 过程。布局模拟结果证明建议 S 盒子与中等区域惩罚提供低力量的消费和高速度。这研究也证明钟更少设计方法论能实现为无线传感器节点的核心削的高效的密码的知识产权(IP ) 。

英文摘要：

The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.