中文摘要：

在讨论高级加密标准（AES,advanced encryption standard）的算法、电路实现的基础上,通过功耗、面积和速度的折衷完成了用于无线传感器网络的AES协处理器设计.重点讨论了实现设计中面积和功耗优化的问题.采用加密解密复用设计,减小了设计面积.通过分析功耗的瓶颈,采用低功耗的S盒设计和减小组合电路无效翻转的方法进行功耗优化,并给出了功耗仿真的结果.该设计能达到非常快的处理速度,数据率可达到每时钟周期1.33 byte.

英文摘要：

Described were the algorithm and circuitry architecture of low cost advanced encryption standard （AES） implementation for wireless sensor network. The design of AES coprocessor was implemented by trade-offs between power dissipation, area and speed, focusing the optimization of area and power consumption. Module reusing method in encryption and decryption process is proposed to optimize chip area. Some techniques of S-box design and reducing combinational circuit invalid switch are presented to reduce power consumption after analysis of the bottleneck of low power design. The results of the power simulation are demonstrated. The proposed AES coprocessor solution can reach high operation speed at a rate of 1.33 byte per clock cycle.