中文摘要：

设计为低力量的标准(AES ) 密码学嵌入的精力有效的先进加密是关键的以有限电池为动力的系统。自从 S 盒子，消费许多全部的 AES 电路电源，减少 AES 电源消费的一条有效途径在减少 S 盒子电源消费在于。在 S 盒子的各种各样的实现之中，最精力有效的是 decoder-switch-encoder (DSE ) 建筑学。在这篇论文，我们精制 DSE 建筑学并且建议更低的电源的一更快的、更紧缩的 S 盒子体系结构：一改善并且完整平衡的 DSE 建筑学。这体系结构用 0.25 μ m 1.8V UMC 互补金属氧化物半导体技术在 10 MHz 完成 68 μ W 的低电源消费。与原来的 DSE S 盒子相比，它进一步分别地在 8% ， 14% 和 10% 减少延期，门计数和电源消费。在健全时间，模拟结果证明改进 DSE S 盒子以力量区域产品和力量延期产品在各种各样的 S 盒子体系结构之中有最好的表演，并且它为实现低电源 AES 密码学是最佳的。

英文摘要：

It is crucial to design energy-efficient advanced encryption standard （AES） cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switchencoder （DSE） architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power： an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 μW at 10 MHz using 0.25 ktm 1.SV UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respect/vely. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.