中文摘要：

研究了高级加密标准（AES）中不同结构S盒实现的面积、功耗与安全性因素,为资源受限和安全性要求高的嵌入式加密应用场合提供了设计参考依据.基于仿真工具和0.25μm,1.8 V工艺库,完成了包括查找表（LUT）、有限域分解（GF（2^4））、译码交错编码（DSE）等在内的5种S盒结构设计.基于功耗分析攻击,引入了S盒的功耗比率-相关系数积作为安全性指标.仿真结果表明GF结构S盒具有面积小、安全性高等特点,而DSE结构S盒具有极低功耗特性.

英文摘要：

The areas, power consumptions and securities of S-boxes in various very large scale integrate （VLSI） architectures for advanced encryption standard （AES） were analyzed to give a design basis for a VLSI implementation with constrained resource and more secure applications. Different Sbox architectures, including look-up table （LUT）, galois field （GF （24 ））, decoder-switch-encoder （DSE）, were implemented through simulation tools and technology library with 0.25 μm and 1.8 V. The product of power ratio-correlation factor was introduced as a security evaluation to resist power analysis attacks. The experimental results show that the GF solution is characterized by the small-size, high security, and the DSE solution reduces power consumption by a large degree.