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中文摘要：
众所周知，CMOS电路测试时由漏电流引起的漏电流功耗在测试功耗中处于重要地位，降低测试时的漏电流对于延长需要周期性自测试的便携式系统电池寿命、提高测试的可靠性和降低测试成本都至关重要，文章首先分析了漏电流的组成，和与之相关的晶体管的堆栈效应，然后，我们提出了一种基于测试向量中不确定位（X位）、使用遗传算法优化集成电路测试时漏电流的方法，实验结果证明在组合电路和时序电路测试中该方法能够在不影响故障覆盖率的条件下，有效优化测试时电路的漏电流。
英文摘要：
It is well-known that leakage power dissipation caused by leakage current in CMOS circuits during test periods has become a significant part of the total power dissipation. It is important to reduce leakage power to improve battery life in portable systems employing periodic self-test, to increase reliability of test and to reduce test-cost. This paper first analyzes leakage current, and introduces the transistor stacking effect relevant to it. Then, we present a method based on dont care bits （X） in test vectors and using the genetic algorithm to optimize leakage current in IC test. Experimental results indicate that this method can effectually optimize leakage current of combinational circuits and sequential circuits during test, and it doesnt lose fault coverage.
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