中文摘要：

提出了一种嵌入式SRAM的高成品率优化方法：通过增加冗余逻辑和电熔丝盒来代替SRAM中的错误单元。利用二项分布计算最大概率缺陷字数，从而求出最佳冗余逻辑。将优化的SRSRAM64K×32应用到SoC中，并对SRSRAM64K×32的测试方法进行了讨论。该SoC经90nm CMOS工艺成功流片，芯片面积为5．6mm×5．6mm，功耗为1997mw。测试结果表明：优化的SRSRAM64K×32在每个晶圆上的成品数增加了191个，其成品率提高了13．255％。

英文摘要：

In order to optimize embedded SRAM for higher yield, presented is a method of adding redundancy logic and E-FUSE box to replace the faulty units of SRAM in this paper. By means of binomial distribution to count the faulty words of max probability, the optimum redundant logic is calculated. The SR SRAM64K × 32 optimized is used in SoC and the testing method of the SR SRAM64K × 32 is discussed. The SoC design has been successfully implemented in a Chartered 90nm CMOS process. The SoC chip occupies 5.6 mm × 5.6 mm in die area and consumes 1997mW. The testing results indicate that the number of good SR SRAM64 K × 32 per wafer is increased by 191 and the yield gain is 13. 255%.