中文摘要：

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏（SBSD）SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应（FIBL）并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应（FIBS）是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的.

英文摘要：

The impact of high-k dielectrics on the performance of Schottky barrier source/drain （SBSD） ultra-thin body （UTB） SOI is investigated in this paper. With the dielectric constants increasing, the on-state currents of SBSD UTB SOI MOSFET decrease, which suggests that the fringing induced barrier lowering （FIBL） is not the major mechanism for the variation of Schottky barrier height. This phenomenon can be understood in terms of the fringing induced barrier shielding （FIBS）. It is also shown that the influence of high-k dielectrics on the performance is quite different in the cases that source/drain and gate electrode have an offset or overlap. For the device with an overlap, the structure with a low-k interfacial layer between high-k gate dielectric and substrate is quite effective in suppressing the degradation of drive current due to FIBS. However, for the device with an offset, the combination of high-k dielectric spacer with stack gate can significantly improve the on-state current. This fact can be explained in terms of the refraction of lines of electric force from gate electrode at interfaces of two materials with different dielectric constants. These lines of electric force with refraction can concentrate at the source region, thus lowering the barrier heights and improving the drive currents. Besides, it is shown that on-state current has a local maximum in the case that source/ drain and gate electrode has an offset. The structure parameters can be optimized to improve the drive current.