中文摘要：

提出了一种优化的SRAM，它的功耗较低而且能够自我修复．为了提高每个晶圆上的SRAM成品率，给SRAM增加冗余逻辑和E—FUSE box从而构成SRSRAM。为了降低功耗。将电源开启／关闭状态及隔离逻辑引入SR SRAM从而构成LPSR SRAM．将优化的LPSR SRAM64K×32应川到SoC中，并对LPSR SRAM64K×32的测试方法进行了讨论。该SoC经90nm CMOS工艺成功流片，芯片面积为5.6mm×5．6mm，功耗为1997mW．测试结果表明：LPSR SRAM64K×32功耗降低了17.301％，每个晶圆上的LPSR SRAM64K×32成品率提高了13．255％。

英文摘要：

This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.