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中文摘要：
以处理器的TLB（Translation Look-aside Buffer）部件为研究对象，探讨嵌入式处理器TLB部件的高能效设计方法．用龙芯1号这款有代表性的真实处理器为设计模型，通过对功耗、面积、关键路径和性能等多方面的试验分析，提出了新颖的TLB低功耗设计方法．在经过改进后的TLB设计中，TLB部件的RAM部分的面积减少了50％，功耗降低了92．7％，整个TLB部件的面积减少了23．7％，功耗降低了28．5％，而电路延迟几乎没有增加，处理器的性能也没有受到影响．这充分说明改进方案是非常实用而有效的．
英文摘要：
Based on an analysis of design-related factors： Power, area, critical path and performance of Godson-Ⅰ, a low-power Translation Look-aside Buffer （TLB） design is proposed without sacrifice of performance and timing in the paper. Authors introduce the improved TLB design method in three steps. The first step is to reduce power by reducing RAM accessing; the second step is to reduce area by using only one one-port RAM; and the third step is to reduce delay by adjusting critical path. At last, a new TLB design is structured to meet the need of energy efficient system. In this paper, authors modify the Godson-Ⅰ architecture to incorporate the new TLB design and implement the design at the register transaction level （RTL）, and evaluate the design at the gate level using the commercial EDA tools for power, area and timing analysis. These tools can accurately capture the effect of the new design. Using the new design, the following results are achieved. Power of TLB-RAM reduces 92.7% and area of TLB-RAM reduces 50%. The total area of TLB reduces 23.7% and the total power of TLB reduces 28. 5%. Compared with other methods, the hit rate of this design is much higher and the accessing conflict to RAM between ITLB and DTLB is much reduced. The experimental results show that the proposed method is both practical and effective. Although this work targets to Godson-Ⅰ, the proposed methodology should he applicable to other designs.
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