中文摘要：

基于集总式互连线功耗模型，给出一种分布式动态功耗表达式，在此基础上，采用非均匀互连线结构，提出了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连动态功耗优化模型。并在 90 nm 和 65 nm CMOS 工艺节点下采用 matlab 软件验证了本文模型的有效性，在工艺约束下同时不牺牲延时、带宽、和面积所提模型能够降低高达 30%左右互连线功耗。该模型适用于大规模集成电路互连优化设计。

英文摘要：

Based on the lumped interconnection power model,a distributed dynamic power model is presented first.Then by adopting a non-uniform interconnection structure,a novel optimal interconnection power model is proposed,which is constrained by delay, bandwidth, area, minimum interconnection width and minimum interconnection space.The validity of the proposed model is verified by 90 nm and 65 nm CMOS technology.The results indicate that the proposed model can reduce power consumption as high as 30%,with the delay,area, bandwidth not deteriorated.The proposed optimal model can be used for the interconnection optimal design in large scale integrated circuits.