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Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory
  • ISSN号:1674-4926
  • 期刊名称:《半导体学报:英文版》
  • 时间:0
  • 分类:TP391.41[自动化与计算机技术—计算机应用技术;自动化与计算机技术—计算机科学与技术] TN386.2[电子电信—物理电子学]
  • 作者机构:[1]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • 相关基金:Project supported by the National Natural Science Foundation of China (Nos. 61474137, 61176073, 61306107).
中文摘要:

This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO.Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration.Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.

英文摘要:

This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3 D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.

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期刊信息
  • 《半导体学报:英文版》
  • 中国科技核心期刊
  • 主管单位:中国科学院
  • 主办单位:中国电子学会 中国科学院半导体研究所
  • 主编:李树深
  • 地址:北京912信箱
  • 邮编:100083
  • 邮箱:cjs@semi.ac.cn
  • 电话:010-82304277
  • 国际标准刊号:ISSN:1674-4926
  • 国内统一刊号:ISSN:11-5781/TN
  • 邮发代号:2-184
  • 获奖情况:
  • 90年获中科院优秀期刊二等奖,92年获国家科委、中共中央宣传部和国家新闻出版署...,97年国家科委、中共中央中宣传部和国家新出版署三等奖,中国期刊方阵“双效”期刊
  • 国内外数据库收录:
  • 俄罗斯文摘杂志,美国化学文摘(网络版),荷兰文摘与引文数据库,美国工程索引,美国剑桥科学文摘,英国科学文摘数据库,日本日本科学技术振兴机构数据库,中国中国科技核心期刊,中国北大核心期刊(2004版),中国北大核心期刊(2008版),英国英国皇家化学学会文摘,中国北大核心期刊(2000版)
  • 被引量:7754