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中文摘要：
随着超大规模集成电路制造技术的快速发展,单个芯片上已能够集成的晶体管数目越来越多.由于各种知识产权芯核集成到一个芯片上,这样给集成电路测试带来了巨大的挑战,测试数据压缩技术能够有效降低对昂贵的ATE性能要求.提出一种对称编码方法,能有效地提高测试数据压缩率,降低测试成本.传统的编码技术采用对0游程或1游程进行编码,但由于ATPG工具生成的测试集中存在大量的无关位（X位）,因此以前编码方法未能有效利用测试集的特征.该方法采用对称计算游程的方法,它同时对提出的4类对称性游程编码,且能减短对应码字长度,有效提高压缩率.实验结果和理论分析表明该方案能较以往方法能取得很好的压缩效果,且能适应多样编码对象,硬件结构简单易行.
英文摘要：
With the rapid development of very large scale integrated circuit （VLSI） manufacturing technologies, more and more transistors can be packed into a single chip. Due to integrating various intellectual-property （IP） cores into a chip, the testing of VLSI is facing enormous challenges. Test data compression techniques based on compression codes are used to reduce ATE memory and test application time and to tackle ATE bandwidth limitation. A new test data compression technique based on symmetry-variable code （SVC） is presented in this paper, which provides significant reduction in test data volume and reduces test cost. Traditional variable-to-variable run length coding techniques based on encoding runs of 0＇s and runs of 1＇s. However, there exist numerous don＇t care bits in the original test set generated by ATPG tool, so the previous methods didn＇t make use of the characteristics of the test set effectively. As proposed method calculates four types of runs presented symmetrically, it can reduce the length of code words of the runs respectively, and increase the compression ratio. Experimental results for ISCAS89 benchmark and theoretical analysis show that SVC code can provide higher test data compression efficiency than previous codes, and have better adaptability to various test sets. The decoder for SVC is simple and easy to achieve.
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