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一种新型的低导通电阻折叠硅SOI LDMOS
  • 期刊名称：半导体学报,2006,27(10):1814-1817
  • 时间：0
  • 分类：TN386[电子电信—物理电子学]
  • 作者机构：[1]电子科技大学IC设计中心,成都610054
  • 相关基金：国家自然科学基金资助项目（批准号：60436030）
  • 相关项目：单片功率系统集成（PSoC）的基础理论和技术研究
关键词： 折叠硅, SOI, LDMOS, 多数载流子积累, 击穿电压, 比导通电阻, folded silicon , SOI LDMOS, majority-carrier accumulation, breakdown voltage, specific on-resistance
中文摘要：

提出了一种具有折叠硅表面SOI—LDMOS（FSOI—LDMOS）新结构．它是将硅表面从沟道到漏端的导电层刻蚀成相互排列的折叠状，且将栅电极在较薄的场氧化层上一直扩展到漏端．由于扩展栅电极的电场调制作用使FSOI-LDMOS在比一般SOI-LDMOS浓度高的漂移区表面，包括折叠硅槽侧面形成多数载流子积累，积累的多数载流子大大降低了漂移区的导通电阻．并且沟道反型层浓度基于折叠的硅表面而双倍增加，沟道导通电阻降低．通过三维仿真软件ISE分析，这种结构可以在低于40V左右的击穿电压下，获得超低的比导通电阻．

英文摘要：

A new SOI LDMOS with folded silicon （FSOI-LDMOS） is proposed, in which the silicon substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain. The majoritycarrier accumulation layer is formed in the drift region because of the extended gate when the device is in the on state, and the concentration of drift region is higher than that in conventional SOI-LDMOS with the same breakdown voltage due to from the additional electric field modulation. The extra majority-carrier is introduced on the side-wall of the trench, which further reduces the on-resistance of the drift region. In addition the channel density is double due to trenching in the folded channel,which reduces the channel on-resistance. 3D ISE simulation indicates that the ultra-low specific on-resistance is obtained with a breakdown voltage of less than 40V in FSOI-LDMOS.

同期刊论文项目
单片功率系统集成（PSoC）的基础理论和技术研究
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