中文摘要：

提出一个改进的二阶三位噪声耦合过采样调制器，它将量化器前所有的加法运算移动到第2个积分器的前面，并通过引入反馈通道和延时输入信号，使反馈数模转换器的苛刻时序得到缓解。此调制器在0．35vmCMOS工艺下设计并生产，整个调制器使用了两个有源模块。在100kHz信号带宽和12．8MHz时钟频率下，完成了86．4dB的SNDR和95-8dB的DR,3-3V电源电压下，消耗9．84mW。此调制器能满足GSM系统的需求。

英文摘要：

The authors propose an improved 2nd-order 3-bit noise-coupled SDM in which all the summation before quantizer is moved to the input of the 2nd integrator, and time-constraint of the feedback DAC is relaxed by introducing feedback path and delayed input signal. The modulator was designed and fabricated in a 0.35 μm CMOS process using two active blocks. Under 100 kHz signal bandwidth and 12.8 MHz sampling frequency, 86.4 dB SNDR and 95.8 dB DR can be reached dissipating 9.84 mW power from a 3.3 V supply. The modulator can satisfy the requirements of GSM systems.