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纳米工艺下可制造性和成品率驱动的集成电路设计方法学研究
  • 项目名称：纳米工艺下可制造性和成品率驱动的集成电路设计方法学研究
  • 项目类别：重点项目
  • 批准号：60736030
  • 申请代码：F040205
  • 项目来源：国家自然科学基金
  • 研究期限：2008-01-01-2011-12-31
  • 项目负责人：程玉华
  • 负责人职称：教授
  • 依托单位：北京大学
  • 批准年度：2007
中文摘要：

本课题对纳米工艺下可制造性和成品率驱动的集成电路设计方法学及所需要的互连和器件工艺特性表征和建模有关问题进行了研究。取得了一系列成果（1）新的互连/器件测试结构；（2）新的测试和参数提取方法；（3）全面描述65nm和40nm工艺/器件特性的测试芯片和测试数据库；（4）基于实测数据及面向DFM应用的工艺参数偏差预测模型；（5）基于统计分析PCA方法和增强的SMIC65nm ITF工艺文件；此外还建立了可预测互连工艺参数corner模型；（6）互连线参数波动性的工艺灵敏度分析和预测器件性能可变性的物理模型；（7）建立了温度意识的优化策略和支持多参照目标和有DFM意识的器件和互连线模型； （8）STI引起的应力波动及对MOS器件特性参数的影响分析；（9）OPC造成的器件不规则形态的分析和等效栅长提取并验证；（10）设计流程和预测电路电学性能和成品率的先进模型技术以及针对tree形结构互连线的统计时序分析算法和软件工具。所开发出的工艺/器件模型、设计流程和基于DFM/DFY的集成电路设计方法学为纳米工艺下集成电路设计奠定了坚实基础。

中文主题词： 可制造性设计；纳米工艺集成电路设计方法学；工艺器件特性表征；工艺器件建模；集成电路设计流程
结论摘要：

英文主题词Design-for-Manufacturing; IC design methodology in nanometer processes; process-device characterization; process-device modeling; IC design flow

成果综合统计
成果类型
数量
  • 期刊论文
  • 会议论文
  • 专利
  • 获奖
  • 著作
  • 14
  • 37
  • 10
  • 0
  • 0
期刊论文
Unified Physical Model of Bipolar Oxide-Based Resistive Switching Memory
Physical-Based Threshold Voltage and Mobility Models Including Shallow Trench Isolation Stress Effec
Simulation Study of Intrinsic Parameter Fluctuations in Variable-Body-Factor Silicon-on-Thin-Box (SO
Analysis and Optimization of Thermal-Driven Global Interconnects in Nanometer Design
A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes
纳米CMOS工艺下集成电路可制造性设计技术
Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin
The impact of line edge roughness on the stability of a FinFET SRAM.
Variability Induced by Line Edge Roughness in Double-Gate Dopant-Segregated Schottky MOSFETs
An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement
Impact of line-edge roughness on double-gate Schottky-barrier field-effect transistors
A spread spectrum clock generator with a wide frequency and attenuation tuning range based on a thir
会议论文
A High Quality CMOS Power Regulator for a Wireless Endoscope
A Physical-Based Mobility Model Including STI Stress MOSFETs
RDF Effect Induced by Source/Drain Doping in Nano-Scale UTB SOI MOSFET with Nominally Un-doped Chann
Design of wide power supply, high performance voltage regulator with BCD process
Source/Drain Doping Induced Vth Variation in Nano-scale UTB SOI MOSFET
Site-Site Wireless Power Transmission for Medical Endoscopes
An Overview of Process/Device Modeling Efforts for DFM in advanced CMOS Technology
A Study of Advanced Modeling Methodology of CMOS-compatible RF-MEMS Devices for Integrated Circuit D
Characterization and Analysis of Pattern Dependent Variation-aware Interconnects for a 65nm Technolo
An Efficient wireless power Transmission System for the Capsule Endoscopy Application
A Study of a10-bit 50MS/s Low Voltage Low Power Pipelined ADC
A Charge Pump Circuit Design Based on a 0.35um BCD Technology for High Voltage Driver Applications
Equalization Techniques for High-speed Serial Interconnect Transceivers
A Novel Super-Halo Doping Concept for Nanoscale CMOS Technology
Design For Manufacturing (DFM) in Nano-CMOS Era
Impact of stochastic mismatch on FinFETs SRAM cell induced by process variation
Influence of contact positioning on the performance of stress induced MOSFETs
3-D simulation of geometrical variations impact on nanoscaleFinFETs
A Simple Nano-Scale Patterning Technology for FinFET Fabrication
Variability in Nano-Scale Intrinsic Silicon-on-Thin-Box MOSFETs (SOTB MOSFETs)
Modeling of Variability in Geometric Parameters of MOSFETs for DFM Applications
110W High Power LED Street Lamp Power Driver
Variability in Variable-Body-Factor Silicon-on-Thin-Box MOSFETs (SOTB MOSFETs)
Development of a MEMS/IC Design Environment for RFIC applications
Analysis and Optimization of High-Voltage Devices in a BCD Process
Wafer-Area-Saving Test Structures and Measurement Method for The Characterization of Interconnect Re
Variability Induced by Line Edge Roughness in Intrinsic Silicon-on-Thin-Box (SOTB) MOSFETs
Design and Optimization of Power Devices in a BCD Process
Characteristic Variations Induced by Random Fluctuation of Source/Drain Lateral Distribution Dopant
A 10-bit 1.2V high speed current-steering DAC using a novel switching scheme
VLSI Implementation of Color Interpolation in Color Difference Spaces
A 6-bit 2GS/s 1.2V 78mW Flash ADC in 65nm CMOS
An Efficient and Staible Power Management Cricuit with High Output Energy for wireless powering Caps
Analysis and architecture design of block matching in BM3D image denoising
Interconnect Capacitance Characterization based on Charge Based Capacitance Measurement (CBCM) Techn
High-speed Serial Interconnect Transceiver: Applications and Design
Full 3-D simulation of gate line edge roughness impact on sub-30 nm FinFETs
专利
电流检测方法及电路
互连线电阻电容的测量结构和方法
金属互联线厚度和宽度的测试结构和测试方法
电容测试方法
可节约测试成本的集成电路互联线电阻电容测试结构和测试方法
ITF电容参数的提取结构和方法
通孔电阻测量结果及方法
互连线有源器件测试结构及方法
互连线RC工艺角建模方法
互联电阻测量结构及方法
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