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中文摘要：
本课题面向逻辑和存储电路应用及不同集成电路技术代要求,基于CMOS工艺平台,研究了新型围栅纳米线逻辑器件和新型非挥发存储器件及相关物理问题和器件特性。提出了新的基于微电子加工工艺实现围栅纳米线器件的方法,研制出直径10nm的体硅围栅纳米线器件,器件电流开关比达到当时国际报道的同类器件最高值；并且首次制备出基于围栅器件的电流镜电路。系统研究了围栅器件的载流子输运特性、热特性、涨落性、射频/模拟特性、寄生效应、噪声特性以及特殊陷阱行为引起的可靠性问题等,发现了该新结构器件中的系列新现象,提出了相关优化设计方法。在可与逻辑融合的非挥发存储器件研究方面,提出并制备出新的自对准分裂栅垂直浮栅闪存器件,可有效提高注入效率、降低编程功耗,并且工艺简单。提出并制备出新型垂直沟道分离陷阱闪存器件（VDNROM）,提出兼容性集成工艺,可实现每单元4位存储。面向嵌入式应用,提出并在标准工艺线成功实现了新型金属插指耦合存储单元结构和叠层金属耦合单元结构,可提高擦写速度,降低擦写电压,保持较好的耐久性。提出并研制出全兼容型的基于富硅氧化层的阻变存储器件,具有很好的嵌入式应用潜力,为纳米集成电路技术发展奠定了基础
结论摘要：
英文主题词logic device,gate-all-around nanowire transistors, device characterization, nonvolatile memory devices,resistance change memory devices
成果综合统计
期刊论文
会议论文
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著作
期刊论文
A control-gate-assisted erasing method for a single-poly EEPROM cell with metallic control gate stru
Investigation on Self-Heating Effect in Gate-All-Around Silicon Nanowire MOSFETs From Top-Down Appro
Random telegraph signal noise in gate-all-around silicon nanowire transistors featuring Coulomb-bloc
Investigations on the physical limitation and electrostatic improvement of a gate-all-around silicon
A model for radiation-induced off-state leakage current in N-channel metal-oxide-semiconductor trans
Effective crosstalk isolation with post-CMOS selectively grown porous silicon technique for radio fr
A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed ch
Characteristics and fluctuation of negative bias temperature instability in Si nanowire field-effect
Novel Thermally Stable Single-Component Organic-Memory Cell Based on Oxotitanium Phthalocyanine Mate
Investigation of the off-state behavior in deep-submicron NMOSFETs under heavy ion irradiation by 3D
High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulati
Characteristics of Gate Current Random Telegraph Signal Noise in SiON/HfO2/TaN p-Type Metal-Oxide-Se
High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structu
Deteriorated radiation effects impact on the characteristics of MOS transistors with multi-finger co
The Combined Impact of Total Ionizing Dose Effect and Negative Bias Temperature Stress on Deep Sub-M
Forming-less Unipolar TaOx-based RRAM with Large CC-independence Range for High Density Memory Appli
Flexible single-component-polymer resistive memory for ultrafast and highly compatible nonvolatile m
Performance improvement of the EEPROM cells with the standard logic process featuring a metal finger
Negative-bias temperature instability in gate-all-around silicon nanowire MOSFETs: Characteristic mo
A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and heli
Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency an
High-performance integrated inductor and effective crosstalk isolation using post-CMOS selective gro
Spontaneously formed closed rings of single-wall carbon nanotube bundles and their physical mechanis
会议论文
The material characterization of nickel germanosilicides on SiGe/Si substrate and the contact size e
A comprehensive study on schottky barrier nanowire transistors (SB-NWTs): Principle, physical limits
Theoretical study of low-energy electron penetration in resist-substrate target by Monte Carlo simul
Reliability enhancement in advanced MOSFETs Using the U—shape STI structure for radiation applicatio
Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of se
Investigation of the RESURF dielectric inserted (REDI) LDMOS as a novel silicon-based RF power devic
Impacts of non-negligible electron trapping/detrapping on the NBTI characteristics in silicon nanowi
A new highly-scalable equivalent circuit model for on-chip symmetrical transformer with accurate sub
Investigations on the physical understanding of mobility in MOSFETs - From drift-diffusion to quasi-
Study of Low Frequency Noise Behavior in Silicon Nanowire Transistors Fabricated with Top—to—Down Ap
An Experimental Study on Carrier Transport in Silicon Nanowire Transistors: How Close to the Ballist
Self-Heating Effect and Characteristic Variability of Gate-All-Around Silicon Nanowire Transistors f
The Impact of Pre—Ion Implantation （PII） on the Characteristics of Nickel Germanide Films and NiGe/G
Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire M
Predictive Modeling of Capacitance and Resistance in Gate-all-around Cylindrical Nanowire MOSFETs fo
Impacts of Diameter-Dependent Annealing on S/D Extension Random Dopant Fluctuations in Silicon Nanow
High-Q integrated inductor using Post-CMOs selectively grown porous silicon (SGPS) technique for RFI
New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CM
Precise Simulation on Ultra-Low Energy Ion Implantation by Molecular Dynamic Approach with Proper In
A molecular dynamic simulation on boron monomer and boron cluster implantation under line edge rough
A Comparison Study of Silicon Nanowire Transistor with Schottky-Barrier Source/Drain and Doped Sourc
New Insights into Oxide Traps Characterization in Gate-All-Around Nanowire Transistors with TiN Meta
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