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中文摘要：
设计一种低温漂低功耗的带隙基准结构,在传统带隙基准核心电路结构上增加一对PNP管,两个双极型晶体管叠加的结构减小了运放的失调电压对输出电压的影响,降低了基准电压的温度失调系数。电路设计与仿真基于CSMC0.5μm CMOS工艺,经流片,测得室温下带隙基准输出电压为1.326 65 V,在-40～＋85℃范围内的温度系数为2.563 ppm/℃;在3.3 V电源电压下,整个电路的功耗仅为2.81μW;在2～4 V之间的电源调整率为206.95 ppm。
英文摘要：
A type of low temperature drift and low power consumption handgap reference circuit are presented. The temperature drift is lowered by adding two PNP transistors to conventional circuit. The effection of OPAMP＇s offset to the output voltage is minimized by the folded bipolar transistors. This bandgap reference circuit delivers an output of 1. 326 65 V at 300 K with temperature coeffience of 2. 563 ppm/℃ between -40- ＋85 ℃. The power dissipation of whole circuit is about 2.81 μW with a source of 3.3 V. And the line regulation of the circuit between 2-4 V is 206.95 ppm.
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