位置：成果数据库 > 期刊 > 期刊详情页
一种应用于流水折叠式A/D转换器的失调抵消预放大器
  • 期刊名称：西安电子科技大学学报，2012年4月，39(2): 114-120
  • 时间：0
  • 分类：TN402[电子电信—微电子学与固体电子学]
  • 作者机构：[1]西安电子科技大学微电子学院,陕西西安710071
  • 相关基金：国家自然科学基金资助项目（60725415,60971066,61006028）; 国家863资助项目（2009AA01Z258）; 陕西省重大技术创新专项资助项目（2009ZKC02-11）
  • 相关项目：集成电路设计（包括ＣＡＤ）
关键词： 失调抵消, 回馈噪声, 预放大器, A/D转换器, 流水折叠, offset cancellation, kickback noise, preamplifier, A/D converters, pipelined folding
中文摘要：

根据流水折叠式A/D转换器的应用要求,设计了一种失调抵消预放大器.采用开关电容电路实现失调存储技术,以减小输入失调电压对转换精度的影响,并通过引入MOS电容实现回馈噪声中和技术.基于SMIC 0.18μm CMOS工艺,在1.8V电源电压、200MHz时钟频率下,对所设计的预放大器进行了功能验证和蒙特卡洛分析.其失调方差仅为3.24mV,功耗为362μW.测试了整个10位100MS/s A/D转换器,最大INL和DNL分别为1.6LSB和0.6LSB.在fin=32MHz,fs=100MHz时,测得SFDR为55dB.

英文摘要：

This paper presents an offset cancellation preamplifier based on the requirement of the pipelined folding A/D converter.The offset storage technique is realized with switched capacitor circuits to eliminate the effect of the input offset voltage on the resolution.The neutralization technique is introduced by MOS capacitors to reduce the kickback noise.In the SMIC 0.18 μm CMOS process,by Mente Carlo simulation the preamplifier with offset variance of 3.24 mV is verified and 362 μW is consumed at 1.8 V and 200 MHz.The measured peak INL and DNL are 1.6 LSB and 0.6 LSB for the 10 bit 100 MS/s A/D converter.SFDR is 55 dB when fin= 32 MHz at fs= 100 MHz.

同期刊论文项目
CMOS数据转换器关键器件匹配性及高层次模型研究
期刊论文 28 专利 3
非标准逻辑数字电路的衬底噪声建模及验证技术研究
期刊论文 53
集成电路设计（包括ＣＡＤ）
期刊论文 136
同项目期刊论文
Circuit modeling and performance analysis of SWCNT bundle 3D interconnects
考虑MOS效应的锥型硅通孔寄生电容解析模型
A high-speed latched comparator with low offset voltage and low dissipation
一种峰值电流控制模式的大功率DC-DC转换器芯片设计
A fast-locking low-jitter pulsewidth control loop for pipelined ADC
A CMOS 4.6 ppm/degrees C curvature-compensated bandgap voltage reference
A new stereo enhancement circuit for class-D amplifier
A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC
A 3.03 uW 10-BIT 200 KS/s SAR ADC IN 0.18 uM CMOS
A novel DC and PWM dual-mode dimming circuit for the WLED driver
A high precision CMOS voltage reference without resistors
A 1.33 μW 10-bit 200KS/s SAR ADC with atri-level based capacitor switching
一种高性能BiCMOS差分参考电压源
A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC
A 10-bit 100-MS/s CMOS Pipelined Folding A/D Converter
Novel hybrid D/A structures for high-resolution SAR ADCs-analysis, modeling and realization
Design of an LED driver based on hysteretic-current-control mode in a 0.6 um BCD process
A high gain wide dynamic range transimpedance amplifier for optical receivers
A programmable MDAC with power scalability
A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC
A clock generator for a high-speed high-resolution pipelined A/D converter
考虑硅通孔的三维集成电路最高层温度模型
Structural, Elastic, and Electronic Properties of a New Phase of Carbon
基于并行完备检测的高速异步流水线设计
一种高速延时无关片上异步转同步通信接口的设计
Low-power variable frequency PFC converters
一种NoC路由器间互连线的自适应驱动方法
A full asynchronous serial transmission converter for network-on-chips
一种基于模糊推理的内插滤波器设计与实现
一种面向彩色CIS数据接口的低功耗编码方法
一种考虑工艺波动的RC互连延时统计模型
CMOS双层可变功函数金属栅技术
一种基于非线性补偿技术的混合模式65nmCMOS带隙基准源
具有部分超结的新型SiC SBD特性分析
一种基于纳米级CMOS工艺的互连线串扰RLC解析模型
基于RLC π型等效模型的互连网络精确焦耳热功耗计算
Statistical Elmore Delay of RC Interconnect Tree
一种R-C-R组合式12位逐次逼近A/D转换器
Improved low-distortion sigma-delta ADC with DWA for WLAN standards.
A self-adaptive full asynchronous bi-directional transmission channel for network-on-chips
A high precision high PSRR bandgap reference with thermal hysteresis protection
双环控制单周期PFC转换器高层次模型及电路
High Voltage REBULF LDMOS with N+-Buried Layer
A Novel low-swing interconnect optimization model with delay and bandwidth constraints
High speed multi-resource arbiter with active virtual channel allocation for network on chips
考虑温度分布效应的非对称RLC树时钟偏差研究
A CMOS Flyback PWM Controller with Low No-Load Power Consumption
高精度音频多位sigma-delta调制器设计
高精度Sigma-delta调制器系统设计和仿真
Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips
一种基于多目标约束的互连线宽和线间距优化模型
考虑热电耦合效应的全芯片温度特性优化方法
一种基于S曲线模型的红外焦平面阵列非均匀性自适应校正算法
An Embedded 1.8V 10bit 120MS/s CMOS Current Steering Digital-to-Analog Converter IP Core
考虑电感效应和工艺波动影响的互连延时建模与计算
无线传感器网络中基于区域通信覆盖的节点定位投放算法
一种改进的高速彩票总线仲裁器
自调整附加权动态仲裁算法
考虑通孔效应和边缘传热效应的纳米级互连线温度分布模型
A high efficiency PWM CMOS class-D audio power amplifier
一种基于目标延迟约束缓冲器插入的互连优化模型
用于片上网络的延时无关异步动态优先级仲裁器
一种高速延时无关同异步转换接口电路
考虑温度分布效应的RLC互连延时分析
基于拓扑划分的片上网络快速映射算法
一种高性能BiCMOS差分参考电压源
An interconnecting bus power optimization method combining interconnect wire spacing with wire order
考虑工艺波动的RC互连树统计功耗
An Interconnect Line Size Optimization Model Considering Scattering Effect
一种0.8V衬底驱动轨对轨运算放大器设计
一种基于标准逻辑单元的GALS异步封装电路
Design of an Integrated 20W×2 Class-D Audio Power Amplifier in 0.8μm BCD Technology
CMOS PWM D类音频功率放大器的过流保护电路
RLC Interconnect Delay with Temperature Distribution Effects
A Novel Interconnect-Optimal Repeater Insertion Model with a Target Delay Constraint
A PWM/Pseudo-PFM Auto-Mode-Applied Buck DC/DC Switching Regulator
A statiscal RCL interconnect delay model taking account of process
D/A Conversion Networks for High-resolution SAR A/D Converters
基于双电源电压和双阈值电压的全局互连性能优化
一种基于延时和带宽约束的纳米级互连线优化模型
处理器可靠性约束的电压频率岛NoC能耗优化
考虑工艺波动影响的RLC互连统计延时
逐次逼近ADC无源器件的匹配性与高层次模型
用于片上网络的准延时不敏感全异步仲裁器
Folded-accumulation LDMOST: new Power MOS Transistor With Very Low Specific On-Resistance.
New Superjunction LDMOS With N-type Charges Compensation Layer
一种考虑温度的分布式互连线功耗模型
A Novel Interconnect-Optimal Repeater Insertion Model with Target Delay Constraint in 65nm CMOS
利用Keating模型计算Si1-xGex及非晶硅的拉曼频偏
A 10-bit 100-MS/s CMOS Pipelined Folding A/D Converter
An Offset Cancellation Technique in a Switched-Capacitor Comparator for SAR ADCs
SHA-less Architecture with Enhanced Accuracy for Pipelined ADC
A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC
一种10位200kS/s 65nm CMOS SAR ADC IP核
考虑工艺波动的两相邻耦合RC互连串扰噪声估计
工艺波动致RLC互连延时极值分析
Optimization design of a full asynchronous pipeline circuit based on null convention logic
考虑热电耦合效应的缓冲器插入功耗优化
考虑互连温度分布的缓冲器插入延时优化方法
一种面向片上网络的多时钟路由器设计
一种低功耗抗串扰的自适应时空总线编码方法
考虑非均匀温度分布的RLC互连延时
一种低能耗的片上网络映射算法
单周期CRM PFC转换器的零交越失真优化设计
A Novel Analytical Thermal Model for Multilevel Nano-scale Interconnects Considering Via Effect.
Low Specific On-Resistance Power MOS Transistor with Multi-Layer Carrier Accumulation breaks the lim
Analysis and modeling of an improved dual-array D/A network for SAR A/D converter
Novel hybrid D/A structures for high-resolution SAR ADCs—analysis, modeling and realization
Three-dimensional global interconnect based on a design window.
Strain coefficient measurement for the (100) uniaxial strain silicon by Raman spectroscopy
A 2.87 ppm/°C 65 nm CMOS bandgap reference with nonlinearity compensation
基于人工蜂群算法的低能耗高性能NOC映射
自适应混沌遗传退火的片上网络映射
一种WSN中的能耗优化动态路由算法
考虑硅通孔的三维集成电路热传输解析模型
用于片上网络的高速低功耗多轨协议异步通信通道
利用Raman光谱测定硅(100)晶面单轴应变的应变系数
基于Simulink的Sigma-DeltaA/D转换器调制器系统建模
PWM降压型DC/DC转换器的高层次模型
虚拟通孔对互连温度变化的影响
应变硅的应变量表征技术
电荷再分配SAR ADC低能耗电容阵列Matlab模型
一种基于0.13m CMOS工艺的10位SAR A/D转换器
深亚微米多层互连的温度分布特性分析
一种考虑温度时间—空间分布的解析互连延时模型
一种抑制总线串扰的自适应时空编码方法
一种0.8V 2.4μA CMOS全差分放大器
A clock generator for a high-speed high-resolution pipelined A/D converter
考虑硅通孔的三维集成电路最高层温度模型
A high performance 90 nm CMOS SAR ADC with hybrid architecture
一种基于0.13μm CMOS工艺的10位SAR A/D转换器
新型高性能分层光片上网络
Improved low-distortion sigma-delta ADC with DWA for WLAN standards
高速环形FIFO的设计
高速自应答异步双轨推通道设计
一种考虑硅通孔电阻-电容效应的三维互连线模型
改进型异质栅对深亚微米栅长碳化硅MESFET特性影响
考虑非均匀温度分布效应的缓冲器插入最优尺寸研究
利用Keating模型计算Si（1-x））Gex及非晶硅的拉曼频移
考虑晶粒尺寸效应的超薄（10—50 nm）Cu电阻率模型研究
基于0．8μm BCD工艺的20W×2集成D类音频功放设计
一种65nm CMoS互连线串扰分布式RLC解析模型
一种PWM/伪PFM双模调制的降压型DC/DC开关电源
一种具有省电模式的CMOS反激式PWM控制器
CMOS PWMD类音频功率放大器的过流保护电路
多性能指标约束的SoC软硬件划分算法
A novel interconnect-optimal repeater insertion model with target delay constraint in 65 nm CMOS
Effect of dummy vias on interconnect temperature variation
基于RLC π型等效模型的互连网络精确焦耳热功耗计算
一种应用于PWM D类音频功率放大器的CMOS Rail-to-Rail比较器
A novel nanometer CMOS interconnect optimal model with target delay and bandwidth constraint
An interconnect width and spacing optimization model considering scattering effect
Three-dimensional global interconnect based on a design window
基于并行完备检测的高速异步流水线设计
An analytical thermal model for 3D integrated circuit considering through silicon via
A 2.87 ppm/degrees C 65 nm CMOS bandgap reference with nonlinearity compensation
A statistical RCL interconnect delay model taking account of process variations
A multilevel nano-scale interconnection RLC delay model
An Interconnect-Line-Size Optimization Model Considering Scattering Effect
一种高速延时无关片上异步转同步通信接口的设计
A full asynchronous serial transmission converter for network-on-chips
A self-adaptive full asynchronous bi-directional transmission channel for network-on-chips
双环控制单周期PFC转换器高层次模型及电路
一种基于多目标约束的互连线宽和线间距优化模型
用于片上网络的延时无关异步动态优先级仲裁器
一种高速延时无关同异步转换接口电路
一种高性能BiCMOS差分参考电压源
一种用于片上网络的延时无关异步动态优先级仲裁器
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
An RLC interconnect analyzable crosstalk model considering self-heating effect
一种基于延时和带宽约束的纳米级互连线优化模型
用于片上网络的准延时不敏感全异步仲裁器
A 10-bit 100-MS/s CMOS Pipelined Folding A/D Converter
一种10位200kS/s 65nm CMOS SAR ADC IP核
A clock generator for a high-speed high-resolution pipelined A/D converter
考虑硅通孔的三维集成电路最高层温度模型
一种基于0.13μm CMOS工艺的10位SAR A/D转换器
FattreeofMesh（FoM） ：一种片上光网络新结构
Improved low-distortion sigma-delta ADC with DWA for WLAN standards
高速环形FIFO的设计
高速自应答异步双轨推通道设计