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中文摘要：
为了能够容忍单粒子多节点翻转，提出了一种新颖的三模互锁加固锁存器。该锁存器使用具有过滤功能的代码字状态保存单元（CWSP）构成三模互锁结构，并在锁存器末端使用CWSP单元实现对单粒子多节点翻转的容错。HSPICE仿真结果表明，相比于三模冗余（TMR）锁存器，该锁存器功耗延迟积（PDP）下降了58．93％；相比于容忍多节点翻转的DNcs—SEU锁器，该锁存器的功耗延迟积下降了41．56％。同时该锁存器具有较低的工艺偏差敏感性。
英文摘要：
In nanometer process, a single event induced multiple upset cannot be ignored. A novel triple interlock hardening latch is proposed for tolerating single event multiple upset. The proposed latch employs code word state preserving （CWSP） cell which has the filtering function to compose triple interlock. At the end of latch, the CWSP cell is also exploited to tolerate single event multiple upset. The simulation results of HSPICE suggest that compared to triple modular redundancy （TMR） latch and DNCS-SEU latch, the power delay product of the proposed latch is reduced by 58.93% and 41.56% respectively. Meanwhile, the proposed latch has less sensitiveness to process variations.
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