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中文摘要：
为了准确评估电路的失效概率,提出一种考虑单粒子多瞬态（SEMT）的数字电路失效概率评估方法.该方法通过解析电路门级网表提取SEMT故障位置对;使用双指数电流源模型模拟故障注人,通过SEMT脉冲复合模型将SEMT脉冲转化为复合的SET脉冲并沿数据通路向下游传播;在脉冲传播过程中,使用SEMT脉冲屏蔽模型评估逻辑屏蔽、电气屏蔽与时窗屏蔽效应,使用电路失效概率计算方法得到电路总体失效概率.实验结果表明,与同类方法相比,文中方法计算结果更为精确;与基于统计的蒙特卡罗方法相比,该方法的相对误差仅为2 % , 能够有效地指导集成电路容错设计.
英文摘要：
To accurately compute the failure probability of digital circuits, a failure probability estimation method considering SEMT is proposed. This approach extracted SEMT fault position pairs by parsing circuit netlist. By using a double exponential current source model, fault injection was simulated on a particle stroked gate. Further, SEMT pulses in a fault position pair were converted to an overlapped SET pulse by means of SEMT pulse com-posite model. By propagating the overlapped SET pulse to downstream gate cells along the data paths, logical masking, electrical masking and timing masking were jointly evaluated with the proposed SEMT pulse masking model. As a result, the overall circuit failure probability was precisely calculated by the proposed failure probabil-ity estimation technique. Experimental results show that the proposed technique is more accurate comparing with the similar method and the relative difference is only 2% comparing with Monte Carlo method, thus the proposed method is valuable to fault tolerance design of ICs for selective hardening.
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