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中文摘要：
工艺尺寸的降低导致组合电路对软错误的敏感性越发突出,由负偏置温度不稳定性（NBTI）效应引起的老化现象越发不容忽视.为了准确地评估集成电路在其生命周期不同阶段的软错误率,提出一种考虑NBTI效应的组合电路软错误率计算方法.首先通过对节点输出逻辑进行翻转来模拟故障注入,并搜索考虑扇出重汇聚的敏化路径;再基于单粒子瞬态（SET）脉冲在产生过程中展宽的解析模型对初始SET脉冲进行展宽,使用NBTI模型计算PMOS晶体管阈值电压增量并映射到PTM模型卡;最后使用考虑老化的HSPICE工具测量SET脉冲在门单元中传播时的展宽,并将传播到锁存器的SET脉冲进行软错误率计算.在考虑10年NBTI效应的影响下,与不考虑NBTI效应的软错误率评估方法相比的实验结果表明,该方法能够平均提高15%的软错误率计算准确度.
英文摘要：
Technology scaling results in that the sensitivity of combinational circuits to soft errors and negative bias temperature instability（NBTI） effect to circuits is becoming more and more serious. In order to accurately compute single event transient（SET） induced soft error rate for combinational circuits in their life time, an aging-aware soft error rate analysis technique for nano-scaled CMOS circuits is proposed. Firstly, fault injection was simulated by means of reversing the output value of a gate cell, and then the related sensitized paths were retrieved by the proposed re-convergence aware sensitized path searching algorithm. Further, width of SET pulses generated in a gate cell was broadened by first-hit SET pulse broadening model, after mapping the PMOS threshold voltages calculated by NBTI models into PTM model cards, broadening ratio of pulses propagating through logic gate cells was measured by aging-aware HSPICE tool. As a result, SER induced by the broadened pulses latched by storage elements was accurately computed. Experimental results show that, the proposed technique improves 15% soft error rate accuracy on average in comparison with the aging-not-aware approach when the target circuits endure 10-years NBTI effect.
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