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中文摘要：
扫描测试是超大规模集成电路测试中最常用的一种技术．但在扫描测试过程中，扫描单元的频繁翻转会引起电路中过大的测试功耗，这对电路测试提出了新的挑战．提出了一种新颖的低功耗全扫描结构——PowerCut，通过对扫描链的修改，加入阻隔逻辑，有效降低扫描移位过程中的动态功耗，同时加入控制单元，使电路在扫描移位过程时进入低漏电流状态，降低了电路的静态功耗．实验表明该结构在较小的硬件开销范围内有效地减小了扫描测试功耗．
英文摘要：
It is obvious that scan testing is the prevalent design for testability （DFT） in very large scale integrated circuits test. However, scan architecture in digital circuits causes much power consumption because when scan vectors are loaded into a scan chain, the effect of scan-ripple propagates to the combinational logic and redundant switching occurs in the combinational gates during the entire vectors shifting period. Hence, low-power design becomes a challenge for scan test. In this paper, a low-power scan architecture-PowerCut is proposed for minimizing power consumption during scan test, which is based on scan chain modification techniques. Blocking logic using transmission gates is inserted into the scan chain to reduce the dynamic power in shift cycle. At the same time, based on minimum leakage vector, a controlling unit is inserted. It makes the circuit slip into low leakage state during shift cycle. Thus, leakage power is also decreased. Experiments results indicate that this architecture can effectually reduce the power during scan test, and it has little improvement in area or delay overhead, compared with other low cost existing methods.
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The Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Micropro
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