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中文摘要：
为了减少测试成本,基于片上数字化的思想,提出复用片上DAC和ADC数模混合片上系统模拟芯核并行测试结构.自保持模拟测试接口可暂存模拟测试激励和测试响应,减少每个测试端口添加的DAC和ADC所产生的额外面积开销,实现芯核级多端口测试和系统级的多核并行测试.采用流水线式并行测试结构减少DAC输出测试激励的等待时间;并进一步分析了模拟测试外壳的测试成本评价方法和优化问题数学模型,在此基础上设计测试成本优化算法,得到优化的模拟测试外壳组分配方案.实验结果表明,文中提出的模拟芯核测试结构对精度的影响小于0.25%,对测试时间可优化40%以上.
英文摘要：
To reduce the huge test cost,based on on-chip virtual digitization method,a parallel test structure for analog cores in mixed-signal SoCs,which using on-chip DAC and ADC,is proposed.The proposed self-hold analog test interface（SHATI）can realize temporal storage of analog test stimuli and test responses,which eliminates the extra silicon overhead caused by DAC and ADC on each test port and enables core-level and system-level parallel test for analog cores.The pipelined parallel test structure can further reduce the waiting time of test stimuli application.Test cost of analog cores is then analyzed and its optimization model is established.Optimized test wrapper groups with minimized test cost can be obtained by proposed optimization algorithm.The experimental results show that the test accuracy error with the proposed test structure is under 0.25% and test time is optimized by 40%.
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同项目期刊论文
The Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Micropro
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