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中文摘要：
基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90nm,65nm和45nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计.
英文摘要：
Optimization of interconnect power and repeater area is an important issue in the design of nanometer CMOS ICs. Based on RLC delay model, the paper proposes a new optimal model to minimize power and area overhead with constraints of target delay and target bandwidth. The proposed model is verified at 90 nm, 65 nm and 45 nm CMOS technology. Experimental result shows that the proposed model can save an average power consumption of 46% and 61% and can save an average area of 65% and 83% at the expense of 1/3 and 1/2 bandwidth, respectively. The proposed optimal model can be used in computer-aided design for nanometer CMOS system-on-chip.
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