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中文摘要：
提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65nm互补金属氧化物半导体（CMOS）工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计.
英文摘要：
Considering the via effect and the heat fringing effect simultaneously,we proposed a compact interconnect temperature distribution model that can be applied for single interconnect and multilevel interconnects.Based on the 65 nm complementary metal-oxide semiconcluctor（CMOS）interconnect and material parameter,the temperature distribution of multilevel interconnects and single interconnect with different lengths was calculated.The results show that the temperature rise of global interconnect is still large when the via effect is considered, while the temperature rise of intermediate line and local line is quite small. For multilevel interconnects, the temperature rise in the uppermost layer interconnect is the largest. The temperature rise is approximately proportional to the thickness of insulator, and will rise higher if the thermal conductivity of dielectric materials becomes smaller. The proposed interconnect temperature distribution model can be used in nanometer CMOS computer-aided design.
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